One of the continuing goals for the semiconductor industry is the production of ever smaller individual devices and resulting denser integrated circuits. In order to produce devices having dimensions which are small enough to meet the requirements of ultra large scale integration (ULSI) both the lateral and vertical dimensions of such devices must be correspondingly reduced. In particular, there is a need for reliable technologies that can be used to both form and contact ultra shallow p-n junctions such as source and drain junctions in MOSFETs, particularly those designed for complimentary metal-oxide-silicon (CMOS) integrated circuits. More specifically, the formation of reliable, high quality, low resistance contacts with p-n junctions shallower than 100 nanometers (nm) is a particular goal.
Presently, such p-n junctions are typically formed by ion implantation followed by silicidation. As is known to those familiar with the manufacture of such devices, ion implantation refers to the process in which appropriate dopant atoms are ionized, accelerated, and directed at a semiconductor material so that the accelerated ions bombard and become implanted in the semiconductor material. Following an annealing step which helps restore the bombarded crystal and activates the implanted dopant atoms, a portion of the semiconductor material results that has a desired conductivity (p or n) that results from the presence of the implanted ions and that is often opposite that of the adjacent non-implanted portions of the semiconductor material. These adjacent p-type and n-type regions define p-n junctions therebetween.
As further known to those familiar with such processes, silicidation is the process of forming a metal-silicon compound for use as a contact with a portion of a device such as a junction. The process is desireable because the resulting silicide composition typically has a lower resistivity than does silicon alone. Silicidation is often carried out by depositing a metal such as titanium, cobalt, or tungsten onto silicon followed by either conventional furnace annealing or rapid thermal annealing to form the metal silicide.
Another goal in the manufacture of such devices and their integrated circuits is to be able to use self-alignment (or "selective") techniques in the manufacturing process. As is known to those familiar with such processes, semiconductor devices, particularly those formed into integrated circuits, are often formed using photolithography techniques and a series of masks to selectively define, deposit, or remove materials such as metals, semiconductors and insulators until a desired device has been produced. When several adjacent layers of materials are processed in this manner, the accuracy and precision required makes the processes expensive and time consuming. Furthermore in some cases even the best available accuracy falls short of physical and electronic requirements.
In self-alignment techniques, portions of an existing structure themselves are used to define the areas where other materials will be deposited or other processes will take place. This helps eliminate the use of a separate mask and lithography step for one or more of the manufacturing steps. For example, a MOSFET (metal-oxide-semiconductor field effect transistor) can be produced using self-alignment techniques once an appropriate gate structure is in place. Such a gate structure on a silicon substrate will mask the underlying silicon substrate from the effects of ion implantation. Thus, in producing a self-aligned MOSFET, the portions of the silicon substrate adjacent the gate structure are doped by ion implantation while the substrate below the gate structure is not. The result is a "self-aligned" source and drain produced without an additional masking step.
In a typical MOSFET process, polysilicon is deposited over the gate oxide, and then the polysilicon and the oxide are patterned together to form the aligned gate structure. The self-aligned source and drain are then formed by ion implantation and anneal. Polysilicon can, of course, withstand the annealing temperatures.
Thus, a typical MOS manufacturing process will use polysilicon for the gate electrode to take advantage of self-alignment techniques, followed by an ion implant and anneal cycle and a silicidation step to form appropriate metallized contacts to the source and drain.
Silicidation of silicon, however, raises associated disadvantages and difficulties in the production of ever smaller devices. In particular, the nature of the silicidation process causes a significant amount of silicon to be consumed below the gate oxide-silicon interface level. During the process silicide is formed from the chemical reaction between the deposited metal and the underlying silicon. This typically unavoidably results in the consumption of the silicon below the gate oxide level of a structure such as a MOS transistor. This silicon consumption during the silicidation process can lead to large leakage currents and even device failure. As an illustrative example, when a 10 nm layer of titanium is deposited and then annealed to form titanium silicide, approximately 25 nm of silicon will be consumed. This means that an ultra shallow 75 nm junction will be totally consumed by a titanium layer 30 nm thick used to produce titanium silicide.
A potential solution to this problem has been to selectively deposit additional silicon (either crystalline or polycrystalline) on the substrate over the source and drain portions to form an additional buffer or sacrificial layer between the substrate and the refractory metal that is eventually deposited to form the silicide. This process raises the source and drain junctions and results in what is sometimes referred to as an "UPMOS" structure. This process, however, raises yet other disadvantages. Selective deposition of silicon requires higher temperatures and may employ or produce hydrochloric acid (HCl) in the process, which in turn may damage the structure. Also, dopant diffusion can often take place at the temperatures required to deposit the silicon layer, thus compromising or destroying device performance. Finally, selective deposition of silicon for this application is generally difficult to achieve from a technical standpoint and is thus desirably avoided.
There thus exists the need for techniques for producing ultra shallow devices which incorporate the advantages of low resistance offered by silicides, but which avoid the consumption of silicon during silicide formation that otherwise makes the process destructive of the device being manufactured.
There thus exists the need for a method of producing devices in a self-aligned fashion at moderate temperatures which do not affect the other characteristics of the device and at overall lower or more efficient thermal budgets and that support the ability to produce lower resistivity contacts with the appropriate portions and junctions using compounds of refractory metals.